View ISL8033_2988027.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ISL8033, ISL8033a dual 3a low quiescent cu rrent high efficiency synchronous buck regulator ISL8033, ISL8033a ISL8033 is a dual integrated power controller rated for 3a per channel with a 1mhz step-down regulator that is ideal for any low power low-voltage applications. the ISL8033a offers 2.5mhz op eration for smaller more compacted design. the channels are 180 out-of-phase for input rms current and emi reduction. it is optimized for generating low output voltages down to 0.8v each. the supply voltage range is from 2.85v to 6v, allowing for the use of a single li+ cell, three nimh cells or a regulated 5v input. it has a guaranteed minimum output current of 3a each when iset is connected to vdd. the output current of each output is selectable by setting iset pin. the ISL8033, ISL8033a includes a pair of low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external component count. 100% duty-cycle operation allows less than 250mv dropout voltage at 3a. the ISL8033, ISL8033a offers an independent 1ms power-good (pg) timer at power-up. when shutdown, ISL8033, ISL8033a discharges the output capacitor. other features include internal digital soft-start, enable for power sequence, controllable soft-stop output discharge during disabled, start-up with pre-biased output, 100% maximum duty cycle for lowest dropout, 100% duty cycle operation for smooth transition, less than 8a logic controlled shutdown current, independent enable, overcurrent protection, and thermal shutdown. the ISL8033, ISL8033a is offered in a 24 ld 4mmx4mm qfn package with 1mm maximum height. the complete converter occupies less than 5.46cm 2 area. features ? dual 3a high efficiency synchronous buck regulator with up to 95% efficiency ? 2% output accuracy over-temperature/load/line ? internal digital soft-start - 1.5ms ? external synchronization up to 6mhz (ISL8033) ? internal current mode compensation ? peak current limiting and hiccup mode short circuit protection ? adjustable peak overload current ? negative current protection ? pb-free (rohs compliant) applications* (see page 16) ? dc/dc pol modules ?c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ? test and measurement systems ? li-ion battery power devices ? bar code readers efficiency vs load 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) efficiency (%) 3.3v out v in = 5v caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. october 21, 2010 fn6854.1
2 fn6854.1 october 21, 2010 typical application circuit l1 1.5h lx1 pgnd fb1 vin1, 2 en1 pg1 sync input 2.85v to 6v output1 1.8v/3a c1 2x22f ISL8033 c2 r2 124k r3 100k 2x22f vdd sgnd c3 12pf l2 1.5h fb2 output2 1.8v/3a c4 r5 124k r6 100k 2x22f c5 12pf lx2 pgnd sgnd en2 pg2 iset figure 1. typical application diagram - dual independent outputs table 1. ISL8033 component value selection v out 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v c1 2x22f 2x22f 2x22f 2x22f 2x22f 2x22f c2 (or c4) 2x22f 2x22f 2x22f 2x22f 2x22f 2x22f c3 (or c5) 12pf 12pf 12pf 12pf 12pf 12pf l1 (or l2) 1.0h~2.2h 1.0h~2.2h 1.0h~2.2h 1.0h~3.3h 1.0h~3.3h 1.0h~4.7h r2 (or r5) 0 50k 87.5k 124k 212.5k 312.5k r3 (or r6) 100k 100k 100k 100k 100k 100k table 2. ISL8033a component value selection v out 0.8v 1.2v 1.5v 1.8v 2.5v 3.3v c1 2x22f 2x22f 2x22f 2x22f 2x22f 2x22f c2 (or c4) 2x22f 2x22f 2x22f 2x22f 2x22f 2x22f c3 (or c5) 12pf 12pf 12pf 12pf 12pf 12pf l1 (or l2) 0.47~1.5h 0.47~1.5h 0.47~1.5h 0.47~1.5h 1.0~2.2h 1.0~3.3h r2 (or r5) 0 50k 87.5k 124k 212.5k 312.5k r3 (or r6) 100k 100k 100k 100k 100k 100k note: the minimum output capacitor value is given for different output voltage to make sure the whole converter system is stable. output capacitance should increase to support faster load transient requirement. table 3. summary of differences part number switching frequency ISL8033 internally fixed switching frequency f sw = 1mhz ISL8033a internally fixed switching frequency f sw = 2.5mhz ISL8033, ISL8033a
3 fn6854.1 october 21, 2010 block diagram lx1 + + csa1 + + + slope comp soft- start 0.8v eamp comp pwm logic controller protection driver fb1 + 0.736v 0.864v pg1 sync shutdown vin pgnd oscillator + bandgap scp + 0.5v en1 shutdown 1ms delay 0.3pf 27pf 390k sgnd 3pf 1.6k lx2 + + csa2 + + + slope comp sta rt soft- start 0.8v eamp comp pwm logic controller protection driver fb2 + 0.736v 0.864v pg2 shutdown vin pgnd + bandgap scp + 0.5v en2 shutdown 1ms delay 0.3pf 27pf 390k sgnd 3pf 1.6k 1m thermal shutdown shutdown vin 1m vin ocp threshold logic iset ISL8033, ISL8033a
4 fn6854.1 october 21, 2010 pin configuration ISL8033, ISL8033a (24 ld qfn) top view lx2 pgnd2 pgnd2 pgnd1 pgnd1 lx1 nc nc fb1 sgnd pg1 sync lx2 vin2 vin2 en2 pg2 fb2 lx1 vin1 vin1 vdd iset en1 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 25 pd pin descriptions pin number symbol description 1, 24 lx2 switching node connection for channel 2. connect to one terminal of inductor for vout2. 22, 23 pgnd2 negative supply for the power stage of channel 2. 4 en2 regulator channel 2 enable pin. enable the ou tput, vout2, when driven to high. shutdown the vout2 and discharge output capacitor when driv en to low. do not leave this pin floating. 5 pg2 1ms timer output. at power-up or en hi, this output is a 1ms delayed power-good signal for the vout2 voltage. 6 fb2 the feedback network of the channel 2 regulator. fb2 is the negative input to the transconductance error amplifier. the output voltage is set by an external resistor divider connected to fb2. with a properly selected divide r, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.8v reference. there is an internal compensation to meet a typical application. in addition, the regulator power-good and underv oltage protection circuitry use fb2 to monitor the channel 2 regula tor output voltage. 7, 8 nc no connect pins. please tie to ground. 9 fb1 the feedback network of th e channel 1 regulator. fb1 is the negative input to the transconductance error amplifier. the output voltage is set by an external resistor divider connected to fb1. with a properly selected divide r, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.8v re ference. there is an internal compensation to meet a typical application. in addition, the regulator power-good and underv oltage protection circuitry use fb1 to monitor the channel 1 regula tor output voltage. 10 sgnd system ground. make a single poin t connection from these pins to pgnd. 11 pg1 1ms timer output. at power-up or en hi, this output is a 1ms delayed power-good signal for the vout1 voltage. 12 sync connect to logic high or input voltage vin. conn ect to an external functi on generator for external synchronization. negative edge trigge r. do not leave this pin floating. do not tie this pin low (or to sgnd). 13 en1 regulator channel 1 enable pi n. enable the output, vout1, when driven to high. shutdown the vout1 and discharge output capacitor when driv en to low. do not leave this pin floating. ISL8033, ISL8033a
5 fn6854.1 october 21, 2010 14 iset iset is the output current limit setting of the regulators. see the ?electrical specifications? table on page 6 for settings. 15 vdd input supply voltage for the logic. connect vin pin. 20, 21 pgnd1 negative supply for the power stage of channel 1. 18, 19 lx1 switching node connection for channel 1. connect to one terminal of inductor for vout1. 2, 3, 16, 17 vin2, vin1 input supply voltage. connect a 22f cerami c capacitor to power-ground per channel. 25 pd the exposed pad must be connected to the pgnd pin for proper electrical performance. add as much vias as possible under this pad for opti mal thermal performance. pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL8033irz* 80 33irz -40 to +85 24 ld 4x4 qfn l24.4x4d ISL8033airz* 80 33airz -40 to +85 24 ld 4x4 qfn l24.4x4d notes: 1. add ?-t? suffix for tape and reel.please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL8033 , ISL8033a . for more information on msl, please see technical brief tb363 . ISL8033, ISL8033a
6 fn6854.1 october 21, 2010 absolute maximum ratings (reference to sgnd) thermal information vin1,vin2, vdd. . . . . . . . -0.3v to 6.5v (dc) or 7v (20ms) lx1, lx2. . . -1.5v (100ns)/-0.3v (dc) to 6.5v (dc) or 7v (20ms) en1, en2, pg1, pg2, sync, iset . . . . . . . . . -0.3v to +6.5v fb1, fb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v nc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v esd ratings human body model (tested per jesd22-a114) . . . . . . 4kv charged device model (tested per jesd22-c101e) . . . 2kv machine model (tested per jesd22-a115) . . . . . . . . 0.3kv latch up (tested per jesd-78a; class 2, level a) . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 4x4 qfn package (notes 4, 5) . . . 36 2 junction temperature range . . . . . . . . . . -55c to +150c storage temperature range . . . . . . . . . . . -65c to +150c ambient temperature range . . . . . . . . . . . -40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions vin supply voltage range . . . . . . . . . . . . . . . . 2.85v to 6v load current range per channel. . . . . . . . . . . . . . 0a to 3a junction temperature range . . . . . . . . . . -55c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, the typical specificatio ns are measured at the following conditions: t a = -40c to +85c, v in = 3.6v, en1 = en2 = vdd, l = 1.5h, c1 = c2 = c4 = 2x22f, i out1 = i out2 = 0a to 3a. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 7) typ max (note 7) units input supply vin undervoltage lockout threshold v uvlo rising 2.5 2.85 v hysteresis 50 100 mv quiescent supply current i vdd sync = vdd, en1 = en2 = vdd, f s = 1mhz, no load at the output 15 40 ma sync = vdd, en1 = en2 = vdd, f s = 2.5mhz, no load at the output 30 70 ma shutdown supply current i sd vdd = 6v, en1 = en2 = sgnd 8 20 a output regulation fb1, fb2 regulation voltage v fb 0.790 0.8 0.810 v fb1, fb2 bias current i fb vfb = 0.75v 0.1 a load regulation sync = vdd, output load from 0a to 3a 2 mv/a line regulation vin = vo + 0.5v to 6v (minimal 2.85v) 0.1 %/v soft-start ramp time cycle 1.5 ms compensation error amplifier trans-conductance 20 a/v trans-resistance rt 0.18 0.2 0.22 overcurrent protection dynamic current limit on-time t ocon 17 clock pulses dynamic current limit off-time t ocoff 8 ss cycle positive peak overcurrent limit i poc1 iset = vdd 4.1 4.8 5.5 a i poc2 4.1 4.8 5.5 a i poc1 iset = float 4.1 4.8 5.5 a i poc2 2.7 3.3 3.9 a i poc1 iset = gnd 2.7 3.3 3.9 a i poc2 2.7 3.3 3.9 a ISL8033, ISL8033a
7 fn6854.1 october 21, 2010 ISL8033, ISL8033a negative peak overcurrent limit i noc1 -3.5 -2.5 -1.5 a i noc2 -3.5 -2.5 -1.5 a lx1, lx2 p-channel mosfet on-resistance vin = 6v, i o = 200ma 50 75 m vin = 2.85v, i o = 200ma 70 100 m n-channel mosfet on-resistance vin = 6v, i o = 200ma 50 75 m vin = 2.85v, i o = 200ma 70 100 m lx_ maximum duty cycle 100 % pwm switching frequency f s ISL8033 0.88 1.1 1.32 mhz ISL8033a 2.15 2.5 2.85 mhz synchronization range f sync ISL8033 (note 6) 2.64 6 mhz channel 1 to channel 2 ph ase shift rising edge to rising edge timing 180 lx minimum on-time sync = high (forced pwm mode) 140 ns soft discharge resistance r dis en = low 80 100 120 lx leakage current pulled up to 6v 0.1 1 a pg1, pg2 output low voltage sinking 1ma, vfb = 0.7v 0.3 v pg_ pin leakage current pg = vin = 6v 0.01 0.1 a internal pgood low rising threshold per centage of nominal regulation voltage 89.5 92 94.5 % internal pgood low falling threshold percentage of nominal regulation voltage 85 88 91 % delay time (rising edge) 1ms internal pgood delay time (falling edge) 7 10 s en1, en2, sync logic input low 0.4 v logic input high 1.5 v sync logic input leakage current i sync pulled up to 6v 0.1 1 a enable logic input leakage current i en pulled up to 6v 0.1 1 a thermal shutdown 150 c thermal shutdown hysteresis 25 c notes: 6. the operational frequency per switching channel will be half of the sync frequency. 7. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and ar e not production tested. electrical specifications unless otherwise noted, the typical specificatio ns are measured at the following conditions: t a = -40c to +85c, v in = 3.6v, en1 = en2 = vdd, l = 1.5h, c1 = c2 = c4 = 2x22f, i out1 = i out2 = 0a to 3a. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units
8 fn6854.1 october 21, 2010 typical operating performance ISL8033 unless otherwise noted, operating conditions are: t a =+25c, v in = 5v, en = v in , l1 = l2 = 1.5h, c1 = c2 = c4 = 2x22f, v out1 =1.2v, v out2 = 1.8v, i out1 = i out2 = 0a to 3a. figure 2. efficiency, t a = +25c v in = 3.3v figure 3. efficiency, t a = +25c, v in = 5v figure 4. power dissipation, t a = +25c v out =1.8v figure 5. load regulation, v out = 1.2v t a = +25c figure 6. load regulation, v out = 1.5v t a =+25c figure 7. load regulation, v out = 1.8v t a = +25c 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) efficiency (%) 1.5v out 1.2v out 2.5v out 1.8v out 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) efficiency (%) 1.5v out 1.2v out 2.5v out 1.8v out 3.3v out 0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) pd (w) 3.3v in 5v in 1.180 1.185 1.190 1.195 1.200 1.205 1.210 0 0.5 1.0 1.5 2.0 2.5 3.0 iout (a) v out (v) 3.3v in 5v in 1.470 1.475 1.480 1.485 1.490 1.495 1.500 0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) v out (v) 3.3v in 5v in 1.770 1.775 1.780 1.785 1.790 1.795 1.800 0.00.51.01.52.02.53.0 i out (a) v out (v) 3.3v in 5v in ISL8033, ISL8033a
9 fn6854.1 october 21, 2010 figure 8. load regulation, v out = 2.5v t a =+25c figure 9. load regulation, v out = 3.3v t a = +25c figure 10. steady state operation at no load channel 1 (pwm) figure 11. steady state operation at no load channel 2 (pwm) figure 12. steady state operation with full load channel 1 figure 13. steady state operation with full load channel 2 typical operating performance ISL8033 unless otherwise noted, operating conditions are: t a =+25c, v in = 5v, en = v in , l1 = l2 = 1.5h, c1 = c2 = c4 = 2x22f, v out1 =1.2v, v out2 = 1.8v, i out1 = i out2 = 0a to 3a. (continued) i out (a) v out ( v ) 2.460 2.465 2.470 2.475 2.480 2.485 2.490 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.3v in 5v in 3.240 3.245 3.250 3.255 3.260 3.265 3.270 0.0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) v out (v) 5v in lx1 2v/div v out1 ripple 20mv/div il1 0.5a/div . lx2 2v/div v out2 ripple 20mv/div il2 0.5a/div lx1 2v/div v out1 ripple 20mv/div il1 2a/div lx1 2v/div vout1 ripple 20mv/div il1 2a/div lx2 2v/div v out2 ripple 20mv/div il2 2a/div ISL8033, ISL8033a
10 fn6854.1 october 21, 2010 figure 14. steady state operation with full loads at both channels figure 15. load transient channel 1 (pwm) figure 16. load transient channel 2 (pwm) figure 17. soft-start with no load channel 1 figure 18. soft-start with no load channel 2 figure 19. soft-start at full load channel 1 typical operating performance ISL8033 unless otherwise noted, operating conditions are: t a =+25c, v in = 5v, en = v in , l1 = l2 = 1.5h, c1 = c2 = c4 = 2x22f, v out1 =1.2v, v out2 = 1.8v, i out1 = i out2 = 0a to 3a. (continued) lx1 2v/div v out1 ripple 20mv/div lx2 2v/div v out2 ripple 20mv/div v out1 ripple 50mv/div il1 2a/div v out2 ripple 50mv/div il2 2a/div en1 2v/div v out1 0.5v/div il1 0.5a/div pg 5v/div en2 2v/div v out2 1v/div il2 0.5a/div pg 5v/div en1 2v/div v out1 0.5v/div il1 1a/div pg 2v/div ISL8033, ISL8033a
11 fn6854.1 october 21, 2010 figure 20. soft-start at full load channel 2 figure 21. soft-discharge shutdown channel 1 figure 22. soft-discharge shutdown channel 2 figu re 23. channel 1 steady state operation at no load with frequency = 6mhz figure 24. channel 2 steady state operation at no load with frequency = 6mhz figure 25. channel 1 steady state operation at full load with frequency = 6mhz typical operating performance ISL8033 unless otherwise noted, operating conditions are: t a =+25c, v in = 5v, en = v in , l1 = l2 = 1.5h, c1 = c2 = c4 = 2x22f, v out1 =1.2v, v out2 = 1.8v, i out1 = i out2 = 0a to 3a. (continued) en2 2v/div v out2 1v/div il2 1a/div pg 2v/div en1 2v/div v out1 0.5v/div il1 0.5a/div pg 5v/div en2 2v/div v out2 1v/div il2 0.5a/div pg 5v/div lx1 2v/div v out1 ripple 20mv/div il1 0.2a/div synch 5v/div lx2 2v/div v out2 ripple 20mv/div il2 0.2a/div synch 5v/div lx1 2v/div v out1 ripple 20mv/div il1 2a/div synch 5v/div ISL8033, ISL8033a
12 fn6854.1 october 21, 2010 figure 26. channel 2 steady state operation at full load with frequency = 6mhz figure 27. output short circuit channel 1 figure 28. output short circuit recovery channel 1 figure 29. output short circuit channel 2 figure 30. output short circuit recovery channel 2 typical operating performance ISL8033 unless otherwise noted, operating conditions are: t a =+25c, v in = 5v, en = v in , l1 = l2 = 1.5h, c1 = c2 = c4 = 2x22f, v out1 =1.2v, v out2 = 1.8v, i out1 = i out2 = 0a to 3a. (continued) lx2 2v/div v out2 ripple 20mv/div il2 2a/div synch 5v/div lx1 2v/div v out1 0.5v/div il1 2a/div pg 5v/div lx1 2v/div v out1 0.5v/div il1 2a/div pg 5v/div lx2 2v/div v out2 1v/div il2 2a/div pg 5v/div lx2 2v/div v out2 1v/div il2 2a/div pg 5v/div ISL8033, ISL8033a
13 fn6854.1 october 21, 2010 typical operating performance ISL8033a unless otherwise noted, operating conditions are: t a =+25c, v in = 5v, en = v in , l1 = 0.68h, l2 = 1h, c1 = c2 = c4 = 2x22f, v out1 =1.2v, v out2 = 1.8v, i out1 = i out2 = 0a to 3a. figure 31. efficiency vs load, 1mhz 3.3v in dual ch1 +25c figure 32. efficiency vs load, 1mhz 5v in , dual ch1 +25c figure 33. steady state operation at no load channel 1 figure 34. steady state operation at no load channel 2 figure 35. steady state operation with full load channel 1 figure 36. steady state operation with full load channel 2 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) 2.5v out 1.2v out 1.8v out 1.5v out efficiency (%) 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output load (a) efficiency (%) 1.2v out 1.8v out 1.5v out 2.5v out 3.3v out il1 0.2a/div v out1 ripple 20mv/div lx1 2v/div il2 0.2a/div v out2 ripple 20mv/div lx2 2v/div il1 0.2a/div v out1 ripple 20mv/div lx1 2v/div il2 0.2a/div v out2 ripple 20mv/div lx2 2v/div ISL8033, ISL8033a
14 fn6854.1 october 21, 2010 theory of operation the ISL8033 is a dual 3a step-down switching regulator optimized for battery-powered or mobile applications. the regulator operates at 1mhz fixed switching frequency under heavy load condition. the ISL8033a operates at 2.5mhz to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. the two channels are 180 out-of-phase operation. the supply current is typically only 8a when the regulator is shutdown. pwm control scheme pulling the sync pin hi (>1.5v) forces the converter into pwm mode in the next switching cycle regardless of output current. each of the channels of the ISL8033, ISL8033a employ the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting, as shown in the ?theory of operation? on page 14. the current loop consists of the oscillator, the pwm comparator comp, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current sense amplifier csa1. the gain for the current sensing circuit is typically 0.20v/a. the contro l reference for the current loops comes from the error amplifier eamp of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp-up. when the sum of the current amplifier csa1 (or cs a2 on channel 2) and the compensation slope (0.46v/s) reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 39 shows the typical operating waveforms during the pwm operation. the dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier csa_ output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage control loop. the feedback signal comes from the vfb pin. the soft-start block only affects the operation during the start-up and will be discussed separately. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 390k rc network. the maximum eamp voltage output is precisely clamped to the bandgap voltage (1.172v). figure 37. load transient channel 1 f igure 38. load transient channel 2 typical operating performance ISL8033a unless otherwise noted, operating conditions are: t a =+25c, v in = 5v, en = v in , l1 = 0.68h, l2 = 1h, c1 = c2 = c4 = 2x22f, v out1 =1.2v, v out2 = 1.8v, i out1 = i out2 = 0a to 3a. (continued) il1 2a/div v out1 ripple 50mv/div il2 2a/div v out2 ripple 50mv/div figure 39. pwm operation waveforms v eamp v csa1 duty cycle i l v out ISL8033, ISL8033a
15 fn6854.1 october 21, 2010 synchronization control (ISL8033) the frequency of operation can be synchronized up to 6mhz by an external signal applied to the sync pin. the 1st falling edge on the sync triggered the rising edge of the pwm on pulse of channel 1. the 2nd falling edge of the sync triggers the rising edge of the pwm on pulse of the channel 2. this process alternates indefinitely allowing 180 output phase operation between the two channels. overcurrent protection cas1 and csa2 are used to monitor output 1 and output 2 channels respectively. the overcurrent protection is realized by monitoring the csa output with the ocp threshold logic, as shown in figure 39. the current sensing circuit has a gain of 0.20v/a, from the p-mosfet current to the csa output. when the csa1 output reaches the threshold set by iset, the ocp comparator is tripped to turn off the p-mosfet immediately. the overcurren t function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfets. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1 and the overcurrent condition flag is set from low to high. if, on the subsequent cycle, another overcurrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the regulator will be shutdown under an ov ercurrent fault condition. an overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode with the delay between restarts being 4 soft-start periods. at the end of the fourth soft-start wait period, the fault counters are reset and soft-start is attempted again. if the overcurrent condition goes away prior to the oc fault counter reaching a count of four, the overcurrent condition flag will set back to low. if the negative output current reaches -2.5a, the part enters negative overcurrent protection. at this point, all switching stops and the part enters tri-state mode while the pull-down fet is discharging the output until it reaches normal regulation voltage, then the ic restarts. pg there are two independent power-good signals. pg1 monitors the output channel 1 and pg2 monitors the output channel 2. when powering up, the open-collector power-on reset output holds low for about 1ms after v o reaches the preset voltage. the pg_ output also serves as a 1ms delayed power-good signal. uvlo when the input voltage is below the undervoltage lock out (uvlo) threshold, the regulator is disabled. enable the enable (en) input allows the user to control the turning on or off the regulator for purposes such as power-up sequencing. when the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference and then the soft-start-up will begin. soft start-up the soft start-up eliminates the inrush current during the start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising 1/2 speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the start-up, the output voltage is less than 0.5v; hence the pwm operating frequency is 1/2 of the normal frequency. when the ic ramps up at start-up, it can?t sink current even at pwm mode. discharge mode (soft-stop) when a transition to shutdown mode occurs, or the output undervoltage fault latch is set, its output discharges to pgnd through an internal 100 switch. power mosfets the power mosfets are optimize for best efficiency. the on-resistance for the p-mosfet is typically 50m and the on-resistance for the n-mosfet is typical 50m . 100% duty cycle the ISL8033 features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the ISL8033, ISL8033a can no longer maintain the regulation at the output, the regulator completely turns on the p-mosfet. the maximum drop-out voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. thermal shutdown the ISL8033, ISL8033a has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely s hutdown. as the temperature drops to +125c, the ISL8033, ISL8033a resumes operation by stepping through a soft start-up. applications information output inductor and capacitor selection to consider steady state and transient operation, ISL8033 typically uses a 1.5h output inductor. higher or lower inductor value can be used to optimize the total converter system performance. for example, for a higher output voltage 3.3v applicatio n, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. the inductor ripple current can be expressed in equation 1: i v o 1 v o v in --------- ? ?? ?? ?? ? lf s ? -------------------------------------- - = (eq. 1) ISL8033, ISL8033a
16 fn6854.1 october 21, 2010 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/product_tree the inductor?s saturation current rating needs be at least larger than the peak current. the ISL8033, ISL8033a protects the typical peak current 4.8a. the saturation current needs be over 4.8a for maximum output current application. ISL8033, ISL8033a uses an internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended minimum output capacitor values for the ISL8033, ISL8033a are shown in tables 1 and 2 on page 2. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider, which is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. refer to figure 1. the output voltage programming resistor, r 2 (or r 5 in channel 2), will depend on th e desired output voltage of the regulator. the value for the feedback resistor is typically between 0 and 750k . let r 2 = 124k , then r 3 will be: for better performance, add 12pf in parallel to r 2 . if the output voltage desired is 0.8v, then leave r 3 unpopulated and short r 2 . input capacitor selection the main functions for the input capacitor is to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. one 22f x5r or x7r ceramic capacitor is a good starting point for the input capacitor selection per channel. pcb layout recommendation the pcb layout is a very impo rtant converter design step to make sure the designed converter works well. for ISL8033, the power loop is composed of the output inductor l?s, the output capacitor c out1 and c out2 , the lx?s pins, and the sgnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. the switching node of the converter, the lx_ pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed as closely as possible to the vin pin . also, the ground of the input and output capacitors should be connected as closely as possible. the heat of the ic is ma inly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at leas t 5 vias ground connection within the pad for the best thermal relief. products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: ISL8033 , ISL8033a to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php r 3 r 2 x0.8v v out 0.8v ? ---------------------------------- = (eq. 2) revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you ha ve the latest revision. date revision change 10/12/10 fn6854.1 in table 3 on page 2, corrected f sw for ISL8033 from 1hz to 1mhz 9/29/10 fn6854.0 initial release. ISL8033, ISL8033a
17 fn6854.1 october 21, 2010 ISL8033, ISL8033a package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

▲Up To Search▲

Price & Availability of ISL8033

	To Download ISL8033 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .